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Senior Fpga Engineer
hace 4 semanas
Who is Recruiting from Scratch:
Recruiting from Scratch is a premier talent firm that focuses on placing the best product managers, software, and hardware talent at innovative companies. Our team is 100% remote and we work with teams across the United States to help them hire. We work with companies funded by the best investors including Sequoia Capital, Lightspeed Ventures, Tiger Global Management, A16Z, Accel, DFJ, and more.
If you are a fit, the team will reach out to you about this role or any others that may be a fit for our clients.
Our Client
Our client is a stealth-mode metal 3D printing startup founded on the belief that transforming the way things are made is essential to making the world a better place. Their advanced technology stack lies at the intersection of hardware, software, and data science, creating the foundation for the world’s first fully autonomous and scalable manufacturing system. Their core team hails from several of the world’s most innovative companies such as SpaceX, Hyperloop, and Blue Origin, and they have secured significant funding from several of Silicon Valley’s top venture capital firms.
As a **Senior FPGA Engineer **, you will be responsible for architecting, designing, developing, and integrating critical software and hardware systems (leveraging the Xilinx Zynq Ultrascale MP SoC) to create a custom compute platform that enables the first production scale, fully automated metal 3D printing factory architecture. As a crucial member of the engineering team, you will be responsible for driving the pace of innovation, maximizing development speed, and maintain a standard of excellence within the entire engineering team.
**Responsibilities**:
- Developing new logic components for use on FPGAs.
- Implementing custom algorithms on FPGAs for signal processing.
- Implementing custom controllers on FPGAs.
- Packaging and using IP components in FPGA block diagram design.
- Working both on development boards and in a production environment.
**Basic Qualifications**:
- 5+ years of FPGA development experience.
- Proficient in VHDL or Verilog.
- Familiarity with Xilinx Vivado/Vitis toolchain development environment.
- Able to provide legal proof of identity and authorization to work in the United States, which applies to U.S. citizens and non-U.S. citizens alike.
**Preferred Skills and Experience**:
- BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or related field.
- Experience with Xilinx Zynq Ultrascale MP SoC.
- Experience with embedded software development including embedded Linux and System on Chip (SoC)-based architectures.
- Experience with heterogeneous computing platforms and high-speed data acquisition systems.
- Familiarity with C/C++ or other high-level programming languages.
- Experience working in both Windows and Linux operating systems.
- Familiarity with LabVIEW is a plus.
- Excellent verbal and written communication skills.
**Location**:
They are located in **Hawthorne, CA **in a 35,000 square foot, state of the art facility featuring large open spaces for team collaboration, R&D, and production, as well as easy access to the 405, 105, and 110 freeways. Their facility is in the heart of LA’s vibrant emerging tech eco-system alongside many other high growth start-ups and enterprises. **THIS POSITION IS ONSITE IN **Hawthorn, CA (Los Angeles Area).
**Benefits**
- They have an inclusive and diverse culture that values collaboration, learning, and making deliberate data-driven decisions.
- They offer a competitive compensation package that includes significant equity in the company, as well as a full suite of additional benefits including premium health care (medical, dental, and vision) and life insurance, generous Paid Parental Leave and extended transition back to work for birthing parent, 401K, and PTO.
- Their work environment includes casual dress, flexible work hours, a fully stocked kitchenette, free parking, daily paid-for lunches, and regular catered team-building events.
**Base Salary Range**: $150,000-$220,000
